U.S. Pat. No. 4,823,173, entitled "High Voltage Lateral MOS Structure with Depleted Top Gate Region," issued Jan. 7, 1989, assigned to the assignee of the present application and the disclosure of which is herein incorporated, describes the formation of a drain-extension drift region in a lateral MOS structure in order to increase reverse breakdown voltage and reduce on-resistance. By adding such a lateral drift region to what is otherwise a low voltage structure, the device can be effectively transformed into a substantially increased (reverse breakdown) voltage MOS device.
The incorporation of such a drain extension region into a PMOS device is diagrammatically illustrated in FIG. 1 as comprising an `N over P` lateral drift, drain-extension region 11, which is contiguous with a (P+) drain region 13 and extends along the surface 14 of an N type semiconductor (e.g. silicon) body 10 toward a (P+) source region 12. By an `N over P` lateral drift region is meant that the lateral drift region 11 comprises an upper or topside N-type conductivity portion 11N, which adjoins a lower P-type conductivity portion 11P, so that, in effect the N portion is `over` the P portion. Conversely, by a `P over N` lateral drift region is meant that the lateral drift region comprises an upper P-type conductivity portion which adjoins a lower N-type conductivity portion, so that the P portion is `over` the N portion.
The lateral drift region 11 may extend beneath a thick oxide layer 15 (typically formed by local oxidation) or under a thin (gate) oxide layer 17, with the lower P-type drain extension portion 11P of the N over P region extending to the surface 14 of the N body 10 beneath a gate electrode 16. In effect, the upper N region 11N may be considered as an upper gate and the N body 10 as the lower gate of a JFET, the channel of which is defined by P drain extension portion 11P.
The parameters of the lateral drift region 11 (e.g. doping profile in ions per square centimeter) are predefined such that, in the presence of a reverse bias applied between the drain region 13 and the body 10, P-drift region 11P becomes depleted of charge carriers prior to the occurrence of breakdown field in the depletion layer 19 that spreads from a reverse-biased drain-to-body PN junction 21, particularly at the sharp curvature portion 23 of the junction beneath gate electrode 18, where the total electrical field strength is increased by the presence of the bias applied to the gate. Typically, the doping per unit area of the P drift region portion 11P is a value on the order of 1 to 2.times.10.sup.12 ions/cm.sup.2, while N region portion 11N has a doping on the order of 1.times.10.sup.12 ions/cm.sup.2, in order to satisfy this fully depleted requirement.
The increased doping of P extension portion 11P reduces its resistance by about a factor of two, resulting in a PMOS device having lower on-resistance, since the drain current flows through the P extension portion 11P. The reduction in on-resistance in a PMOS device employed in an analog switching circuit is particularly important, since PMOS switching devices typically occupy approximately three times the semiconductor real estate as NMOS devices. Reducing PMOS size thus decreases die area. It also diminishes the mismatch in capacitance between P and N channel switch devices, because their sizes are more nearly equal, so that charge transfer errors which result from mismatched capacitances are also reduced.
In addition to signal processing applications having a need for high reverse breakdown MOS devices, there are also a number of applications which require CMOS devices having respectively different reverse breakdown characteristics (e.g. moderate voltages on the order of 20-80 volts for analog functions, such as analog switches and multiplexers, and high voltages on the order of 200-1000 volts for analog switching circuits). Because of the diversity of both the types and parametric variations of the device structures, the processes used to form such combined technology architectures are often complex, sometimes requiring upwards of fifteen masking steps to pattern and layout the topology of the wafer. Moreover, since there is both an increase in cost and a decrease in yield as the number of mask steps increases, it is desirable to reduce the number of steps required to incorporate all of the various types of devices that make up a multifunctional signal processing architecture. Unfortunately, conventional wafer processing to provide lateral drift regions customarily involves the use of both a special mask and a special doping step (e.g. ion implantation) exclusively dedicated to the formation of the drift region. As a consequence, there is an increase in both cost and complexity of the manufacturing process.